Jo Engine  9
Jo Sega Saturn Engine
smpc.h
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1 /*
2 ** Jo Sega Saturn Engine
3 ** Copyright (c) 2012-2017, Johannes Fetz (johannesfetz@gmail.com)
4 ** All rights reserved.
5 **
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7 ** modification, are permitted provided that the following conditions are met:
8 ** * Redistributions of source code must retain the above copyright
9 ** notice, this list of conditions and the following disclaimer.
10 ** * Redistributions in binary form must reproduce the above copyright
11 ** notice, this list of conditions and the following disclaimer in the
12 ** documentation and/or other materials provided with the distribution.
13 ** * Neither the name of the Johannes Fetz nor the
14 ** names of its contributors may be used to endorse or promote products
15 ** derived from this software without specific prior written permission.
16 **
17 ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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19 ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
20 ** DISCLAIMED. IN NO EVENT SHALL Johannes Fetz BE LIABLE FOR ANY
21 ** DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
22 ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
23 ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
24 ** ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
26 ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
37 #ifndef __JO_SMPC_H__
38 # define __JO_SMPC_H__
39 
41 typedef enum
42 {
54  EnableCD = 0x8,
56  DisableCD = 0x9,
62  SystemReset = 0xD,
72  SetSMPCMemory = 0x17,
76  EnableReset = 0x19,
78  DisableReset = 0x1A
80 
81 typedef enum
82 {
84  CommandRegister = 0x2010001f,
86  StatusRegister = 0x20100061,
88  StatusFlag = 0x20100063,
90  InputRegister0 = 0x20100001,
91  InputRegister1 = 0x20100003,
92  InputRegister2 = 0x20100005,
93  InputRegister3 = 0x20100007,
94  InputRegister4 = 0x20100009,
95  InputRegister5 = 0x2010000b,
96  InputRegister6 = 0x2010000d,
98  OutputRegister0 = 0x20100021,
99  OutputRegister1 = 0x20100023,
100  OutputRegister2 = 0x20100025,
101  OutputRegister3 = 0x20100027,
102  OutputRegister4 = 0x20100029,
103  OutputRegister5 = 0x2010002b,
104  OutputRegister6 = 0x2010002d,
105  OutputRegister7 = 0x2010002f,
106  OutputRegister8 = 0x20100031,
107  OutputRegister9 = 0x20100033,
108  OutputRegister10 = 0x20100035,
109  OutputRegister11 = 0x20100037,
110  OutputRegister12 = 0x20100039,
111  OutputRegister13 = 0x2010003b,
112  OutputRegister14 = 0x2010003d,
113  OutputRegister15 = 0x2010003f,
114  OutputRegister16 = 0x20100041,
115  OutputRegister17 = 0x20100043,
116  OutputRegister18 = 0x20100045,
117  OutputRegister19 = 0x20100047,
118  OutputRegister20 = 0x20100049,
119  OutputRegister21 = 0x2010004b,
120  OutputRegister22 = 0x2010004d,
121  OutputRegister23 = 0x2010004f,
122  OutputRegister24 = 0x20100051,
123  OutputRegister25 = 0x20100053,
124  OutputRegister26 = 0x20100055,
125  OutputRegister27 = 0x20100057,
126  OutputRegister28 = 0x20100059,
127  OutputRegister29 = 0x2010005b,
128  OutputRegister30 = 0x2010005d,
129  OutputRegister31 = 0x2010005f,
130  PortDataRegister1 = 0x20100075,
131  PortDataRegister2 = 0x20100077,
137 
138 static __jo_force_inline void jo_smpc_write_byte(jo_smpc_memory_address addr, unsigned char data)
139 {
140  (*(volatile unsigned char *)(addr)) = data;
141 }
143 {
144  return (*(volatile unsigned char *)(addr));
145 }
147 {
148  while ((jo_smpc_read_byte(StatusFlag) & 0x1) == 0x1);
149 }
151 {
152  jo_smpc_wait();
154 }
156 {
158  jo_smpc_wait();
159 }
160 
161 #endif /* !__JO_SMPC_H__ */
162 
163 /*
164 ** END OF FILE
165 */
Definition: smpc.h:125
Sets the 4-byte battery-backed memory contained on the SMPC(which is used by the bios for language se...
Definition: smpc.h:72
Definition: smpc.h:107
Resets the System.
Definition: smpc.h:62
Definition: smpc.h:119
Resets and enables Netlink execution.
Definition: smpc.h:58
static __jo_force_inline void jo_smpc_begin_command(void)
Definition: smpc.h:150
static __jo_force_inline unsigned char jo_smpc_read_byte(jo_smpc_memory_address addr)
Definition: smpc.h:142
Input registers for command issuing. Whatever data the SMPC needs for processing command goes here...
Definition: smpc.h:90
Definition: smpc.h:114
Definition: smpc.h:106
Resets and enables the Motorola C68K (sound) CPU.
Definition: smpc.h:50
Definition: smpc.h:131
Definition: smpc.h:108
Definition: smpc.h:115
Changes the system clockspeed.
Definition: smpc.h:64
Disables the CD Block.
Definition: smpc.h:56
Disables the SH-2 Slave CPU.
Definition: smpc.h:48
Definition: smpc.h:116
Disables the Motorola C68K (sound) CPU.
Definition: smpc.h:52
Status Register.
Definition: smpc.h:86
Definition: smpc.h:111
Definition: smpc.h:100
static __jo_force_inline void jo_smpc_end_command(jo_smpc_command command)
Definition: smpc.h:155
Resets and enables the CD Block.
Definition: smpc.h:54
#define __jo_force_inline
force inline attribute (and prevent Doxygen prototype parsing bug)
Definition: conf.h:154
Definition: smpc.h:110
Definition: smpc.h:112
Definition: smpc.h:101
Definition: smpc.h:123
The command that's supposed to be issued by the SMPC.
Definition: smpc.h:84
Definition: smpc.h:120
Definition: smpc.h:94
static __jo_force_inline void jo_smpc_wait(void)
Definition: smpc.h:146
Definition: smpc.h:135
Definition: smpc.h:129
Definition: smpc.h:102
Definition: smpc.h:124
jo_smpc_command
SMPC Commands.
Definition: smpc.h:41
Definition: smpc.h:132
Resets and enables the SH-2 Master CPU.
Definition: smpc.h:44
Definition: smpc.h:96
Definition: smpc.h:126
Disables Netlink execution.
Definition: smpc.h:60
jo_smpc_memory_address
Definition: smpc.h:81
static __jo_force_inline void jo_smpc_write_byte(jo_smpc_memory_address addr, unsigned char data)
Definition: smpc.h:138
Definition: smpc.h:95
Definition: smpc.h:104
Definition: smpc.h:133
Definition: smpc.h:117
Definition: smpc.h:91
Definition: smpc.h:109
Definition: smpc.h:118
Definition: smpc.h:103
Sets the date and time for the RTC.
Definition: smpc.h:70
Definition: smpc.h:113
Definition: smpc.h:134
Definition: smpc.h:127
Definition: smpc.h:122
Resets and enables the SH-2 Slave CPU.
Definition: smpc.h:46
Ouput Register for the command. If it supports it, it'll output any return data here.
Definition: smpc.h:98
Fetches the SMPC status and peripheral data.
Definition: smpc.h:68
Disables NMI requests to be sent when the Reset button is pressed.
Definition: smpc.h:78
Status Flag. Shows the status of the SMPC command. Normally you set this to 1 when issuing out a comm...
Definition: smpc.h:88
Definition: smpc.h:93
Definition: smpc.h:92
Definition: smpc.h:121
Definition: smpc.h:105
Definition: smpc.h:130
Definition: smpc.h:128
Sends an NMI request to the Master SH2.
Definition: smpc.h:74
Definition: smpc.h:99
Enables NMI requests to be sent when the Reset button is pressed.
Definition: smpc.h:76
Changes the system clockspeed.
Definition: smpc.h:66