Jo Engine Sega Saturn constants (addresses, memory sizes, etc). More...

Macros
#define	JO_VDP1_VRAM
	VDP1 VRAM (512 kilobytes).
#define	JO_VDP1_FB
	VDP1 Frame buffer (256 kilobytes).
#define	JO_VDP1_REG
	VDP1 I/O register address.
#define	JO_VDP1_LAST_REG
	Last VDP1 I/O register address.
#define	JO_VDP1_TVMR
	TV mode selection.
#define	JO_VDP1_FBCR
	Controls the frame buffer.
#define	JO_VDP1_PTMR
	Plot trigger.
#define	JO_VDP1_EWDR
	Erase/write color.
#define	JO_VDP1_EWLR
	Erase/write upper-left position.
#define	JO_VDP1_EWRR
	Erase/write lower-right position.
#define	JO_VDP1_ENDR
	Force draw end.
#define	JO_VDP1_EDSR
	Transfer end status.
#define	JO_VDP1_LOPR
	Return the last command table processed.
#define	JO_VDP1_COPR
	Return the current command table processed.
#define	JO_VDP1_MODR
	Mode status.
#define	JO_VDP1_USER_AREA_SIZE
	VDP1 user area size.
#define	JO_VDP1_USER_AREA_END_ADDR
	VDP1 user area end address.
#define	JO_VDP1_TEXTURE_DEF_BASE_ADDRESS
	VDP1 Sprite base address.
#define	JO_VDP2_REG
	VDP2 I/O register address.
#define	JO_VDP2_LAST_REG
	Last VDP2 I/O register address.
#define	JO_VDP2_VRAM
	VDP2 VRAM (512 kilobytes) = A0 + A1 + B0 + B1.
#define	JO_VDP2_VRAM_A0
	VDP2 VRAM Bank A0 (128 kilobytes).
#define	JO_VDP2_VRAM_A1
	VDP2 VRAM Bank A1 (128 kilobytes).
#define	JO_VDP2_VRAM_B0
	VDP2 VRAM Bank B0 (128 kilobytes).
#define	JO_VDP2_VRAM_B1
	VDP2 VRAM Bank B1 (128 kilobytes).
#define	JO_VDP2_CRAM
	VDP2 Color RAM (4 kilobytes).
#define	JO_VDP2_BANK_SIZE
	VDP2 VRAM Bank size (128 kilobytes).
#define	JO_VDP2_NBG0_CEL_ADR
#define	JO_VDP2_NBG0_MAP_ADR
#define	JO_VDP2_NBG1_CEL_ADR
#define	JO_VDP2_NBG1_MAP_ADR
#define	JO_VDP2_TVMD
#define	JO_VDP2_EXTEN
#define	JO_VDP2_TVSTAT
#define	JO_VDP2_TVSTAT_PAL
	TVSTAT: PAL console (50 Hz).
#define	JO_VDP2_VRSIZE
#define	JO_VDP2_HCNT
#define	JO_VDP2_VCNT
#define	JO_VDP2_RAMCTL
#define	JO_VDP2_CYCA0L
#define	JO_VDP2_CYCA0U
#define	JO_VDP2_CYCA1L
#define	JO_VDP2_CYCA1U
#define	JO_VDP2_CYCB0L
#define	JO_VDP2_CYCB0U
#define	JO_VDP2_CYCB1L
#define	JO_VDP2_CYCB1U
#define	JO_VDP2_BGON
#define	JO_VDP2_MZCTL
#define	JO_VDP2_SFSEL
#define	JO_VDP2_SFCODE
#define	JO_VDP2_CHCTLA
#define	JO_VDP2_CHCTLB
#define	JO_VDP2_BMPNA
#define	JO_VDP2_BMPNB
#define	JO_VDP2_PNCN0
#define	JO_VDP2_PNCN1
#define	JO_VDP2_PNCN2
#define	JO_VDP2_PNCN3
#define	JO_VDP2_PNCR
#define	JO_VDP2_PLSZ
#define	JO_VDP2_MPOFN
#define	JO_VDP2_MPOFR
#define	JO_VDP2_MPABN0
#define	JO_VDP2_MPCDN0
#define	JO_VDP2_MPABN1
#define	JO_VDP2_MPCDN1
#define	JO_VDP2_MPABN2
#define	JO_VDP2_MPCDN2
#define	JO_VDP2_MPABN3
#define	JO_VDP2_MPCDN3
#define	JO_VDP2_MPABRA
#define	JO_VDP2_MPCDRA
#define	JO_VDP2_MPEFRA
#define	JO_VDP2_MPGHRA
#define	JO_VDP2_MPIJRA
#define	JO_VDP2_MPKLRA
#define	JO_VDP2_MPMNRA
#define	JO_VDP2_MPOPRA
#define	JO_VDP2_MPABRB
#define	JO_VDP2_MPCDRB
#define	JO_VDP2_MPEFRB
#define	JO_VDP2_MPGHRB
#define	JO_VDP2_MPIJRB
#define	JO_VDP2_MPKLRB
#define	JO_VDP2_MPMNRB
#define	JO_VDP2_MPOPRB
#define	JO_VDP2_SCXIN0
#define	JO_VDP2_SCXDN0
#define	JO_VDP2_SCYIN0
#define	JO_VDP2_SCYDN0
#define	JO_VDP2_ZMXIN0
#define	JO_VDP2_ZMXDN0
#define	JO_VDP2_ZMYIN0
#define	JO_VDP2_ZMYDN0
#define	JO_VDP2_SCXIN1
#define	JO_VDP2_SCXDN1
#define	JO_VDP2_SCYIN1
#define	JO_VDP2_SCYDN1
#define	JO_VDP2_ZMXIN1
#define	JO_VDP2_ZMXDN1
#define	JO_VDP2_ZMYIN1
#define	JO_VDP2_ZMYDN1
#define	JO_VDP2_SCXN2
#define	JO_VDP2_SCYN2
#define	JO_VDP2_SCXN3
#define	JO_VDP2_SCYN3
#define	JO_VDP2_ZMCTL
#define	JO_VDP2_SCRCTL
#define	JO_VDP2_VCSTAU
#define	JO_VDP2_VCSTAL
#define	JO_VDP2_LSTA0U
#define	JO_VDP2_LSTA0L
#define	JO_VDP2_LSTA1U
#define	JO_VDP2_LSTA1L
#define	JO_VDP2_LCTAU
#define	JO_VDP2_LCTAL
#define	JO_VDP2_BKTAU
#define	JO_VDP2_BKTAL
#define	JO_VDP2_RPMD
#define	JO_VDP2_RPRCTL
#define	JO_VDP2_KTCTL
#define	JO_VDP2_KTAOF
#define	JO_VDP2_OVPNRA
#define	JO_VDP2_OVPNRB
#define	JO_VDP2_RPTAU
#define	JO_VDP2_RPTAL
#define	JO_VDP2_WPSX0
#define	JO_VDP2_WPSY0
#define	JO_VDP2_WPEX0
#define	JO_VDP2_WPEY0
#define	JO_VDP2_WPSX1
#define	JO_VDP2_WPSY1
#define	JO_VDP2_WPEX1
#define	JO_VDP2_WPEY1
#define	JO_VDP2_WCTLA
#define	JO_VDP2_WCTLB
#define	JO_VDP2_WCTLC
#define	JO_VDP2_WCTLD
#define	JO_VDP2_LWTA0U
#define	JO_VDP2_LWTA0L
#define	JO_VDP2_LWTA1U
#define	JO_VDP2_LWTA1L
#define	JO_VDP2_SPCTL
#define	JO_VDP2_SDCTL
#define	JO_VDP2_CRAOFA
#define	JO_VDP2_CRAOFB
#define	JO_VDP2_CRAOFB_SPRITE_OFFSET_MASK
	CRAOFB: sprite color RAM address offset bits.
#define	JO_VDP2_CRAOFB_SPRITE_OFFSET(N)
	CRAOFB: sprite color RAM address offset value (0 to 7).
#define	JO_VDP2_LNCLEN
#define	JO_VDP2_SFPRMD
#define	JO_VDP2_CCCTL
#define	JO_VDP2_SFCCMD
#define	JO_VDP2_PRISA
#define	JO_VDP2_PRISB
#define	JO_VDP2_PRISC
#define	JO_VDP2_PRISD
#define	JO_VDP2_PRINA
#define	JO_VDP2_PRINB
#define	JO_VDP2_PRIR
#define	JO_VDP2_RESERVE
#define	JO_VDP2_CCRSA
#define	JO_VDP2_CCRSB
#define	JO_VDP2_CCRSC
#define	JO_VDP2_CCRSD
#define	JO_VDP2_CCRNA
#define	JO_VDP2_CCRNB
#define	JO_VDP2_CCRR
#define	JO_VDP2_CCRLB
#define	JO_VDP2_CLOFEN
#define	JO_VDP2_CLOFSL
#define	JO_VDP2_COAR
#define	JO_VDP2_COAG
#define	JO_VDP2_COAB
#define	JO_VDP2_COBR
#define	JO_VDP2_COBG
#define	JO_VDP2_COBB
#define	JO_WORK_RAM_HIGH
	High work RAM (1 MB): the fastest memory of the CPUs.
#define	JO_WORK_RAM_LOW
	Low work RAM (1 MB): read much slower by the CPUs, no SCU DMA.
#define	JO_WORK_RAM_SIZE
	Size of the high or low work RAM.
#define	JO_WORK_RAM_BOOT_ROM
	ROM BIOS functions.
#define	JO_WORK_RAM_SLAVE_CPU_STACK_AREA
	Slave CPU stack.
#define	JO_WORK_RAM_MASTER_CPU_DEFAULT_STACK
	Master CPU stack (used by the boot ROM).
#define	JO_WORK_RAM_UNKNOWN_USAGE
	IP.BIN and boot ROM work area.
#define	JO_WORK_RAM_USER_PROGRAM_AND_DATA
	User area.
#define	JO_WORK_RAM_ENGINE_WORK
#define	JO_WORK_RAM_USER_PROGRAM_AND_DATA_END
	End of the user area (the free high work RAM after the engine work area is given to jo_malloc()).
#define	JO_WORK_RAM_STACK_TOP
	Master CPU stack (top).
#define	JO_WORK_RAM_STACK_BOTTOM
	Master CPU stack (bottom, 16 KB, see jo.linker).
#define	JO_WORK_RAM_SLAVE_STACK_TOP
	Slave CPU stack (top).
#define	JO_RAM_CARTRIDGE_ID
	Extended RAM cartridge identifier.
#define	JO_RAM_CARTRIDGE_ID_8MBITS
	Extended RAM cartridge identifier: 1 MB (8 Mbits).
#define	JO_RAM_CARTRIDGE_ID_32MBITS
	Extended RAM cartridge identifier: 4 MB (32 Mbits).
#define	JO_RAM_CARTRIDGE_ENABLE
	Extended RAM cartridge: write 1 to enable the RAM (16 bits write).
#define	JO_RAM_CARTRIDGE_ADDRESS
	Extended RAM cartridge: RAM address.
#define	JO_RAM_CARTRIDGE_8MBITS_BANK2_ADDRESS
	Extended RAM cartridge 1 MB: second bank address.
#define	JO_RAM_CARTRIDGE_8MBITS_BANK_SIZE
	Extended RAM cartridge 1 MB: size of a bank.
#define	JO_RAM_CARTRIDGE_32MBITS_SIZE
	Extended RAM cartridge 4 MB: size.
#define	JO_RAM_CARTRIDGE_ASR0
	A-bus timings for the extended RAM cartridge (JO_SCU_ASR0).
#define	JO_RAM_CARTRIDGE_AREF
	A-bus refresh for the extended RAM cartridge (JO_SCU_AREF).
#define	JO_WORK_RAM_ENGINE_WORK_SECTION
	Put a variable in the engine work area (not cleared by the program loader, cleared at startup).
#define	JO_WORK_RAM_ENGINE_WORK_ALIGNED_SECTION
	Engine work area, for a buffer aligned on a big boundary (placed first: no hole in the work area).
#define	JO_SCU_IMS
	SCU interrupt mask register.
#define	JO_BIOS_SCU_IMS
	Copy of the SCU interrupt mask kept by the BIOS (SYS_GETSCUIM): the interrupt handlers of the BIOS write it to JO_SCU_IMS when they return, it must always be equal to the mask written to JO_SCU_IMS.
#define	JO_BIOS_CHANGE_SYSTEM_CLOCK(CLOCK)
	Boot ROM routine that changes the system clock (SYS_CHGSYSCK): 0 = 26.8 MHz (320 and 640 pixels width), 1 = 28.6 MHz (352 and 704 pixels width). The VDPs, the SCU and the slave CPU are reset.
#define	JO_BIOS_SYSTEM_CLOCK_320
	System clock of the 320 and 640 pixels width modes (see JO_BIOS_CHANGE_SYSTEM_CLOCK()).
#define	JO_BIOS_SYSTEM_CLOCK_352
	System clock of the 352 and 704 pixels width modes (see JO_BIOS_CHANGE_SYSTEM_CLOCK()).
#define	JO_SCU_IST
	SCU interrupt status register.
#define	JO_SCU_ASR0
	SCU A-bus set register 0 (CS0 and CS1 access timings).
#define	JO_SCU_AREF
	SCU A-bus refresh register.
#define	JO_SCU_DMA_READ(N)
	SCU DMA level N (0 to 2): read address, write address (or indirect table), byte count, address add, enable, mode.
#define	JO_SCU_DMA_WRITE(N)
#define	JO_SCU_DMA_COUNT(N)
#define	JO_SCU_DMA_ADD(N)
#define	JO_SCU_DMA_ENABLE(N)
#define	JO_SCU_DMA_MODE(N)
#define	JO_SCU_DMA_STATUS
	SCU DMA status register.
#define	JO_SCU_DMA_STATUS_BUSY(N)
	SCU DMA status: level N in operation.
#define	JO_SCU_DMA_ADD_READ4_WRITE2
	SCU DMA add: read address + 4, write address + 2 (B-bus: VDP1, VDP2, sound).
#define	JO_SCU_DMA_ENABLE_START
	SCU DMA enable: enabled and started.
#define	JO_SCU_DMA_MODE_DIRECT
	SCU DMA mode: direct mode, started by JO_SCU_DMA_ENABLE_START.
#define	JO_SCU_DMA_MODE_INDIRECT
	SCU DMA mode: indirect mode (table of transfers: byte count, write address, read address \| 0x80000000 for the last one).
#define	JO_SCU_DMA_INDIRECT_END
	SCU DMA indirect table: end of the table (read address of the last transfer).
#define	JO_SCU_INT_VBLANK_IN
	SCU interrupt mask bits.
#define	JO_SCU_INT_VBLANK_OUT
#define	JO_SCU_INT_HBLANK_IN
#define	JO_SCU_INT_TIMER0
#define	JO_SCU_INT_TIMER1
#define	JO_SCU_INT_SOUND
#define	JO_SCU_INT_SMPC
#define	JO_SCU_INT_SPRITE_END
#define	JO_SCU_INT_ALL
#define	JO_VECTOR_VBLANK_IN
	SH-2 interrupt vectors used by the SCU.
#define	JO_VECTOR_VBLANK_OUT
#define	JO_VECTOR_HBLANK_IN
#define	JO_VECTOR_TIMER0
#define	JO_VECTOR_TIMER1
#define	JO_VECTOR_SOUND
#define	JO_VECTOR_SMPC
#define	JO_VECTOR_SPRITE_END
#define	JO_CACHE_THROUGH(ADDR)
	Cache-through mirror of an address (to share data between the two CPU).
#define	JO_SH2_CCR
	Cache control register.
#define	JO_SH2_CCR_CACHE_ENABLE
	CCR: cache enabled.
#define	JO_SH2_CCR_CACHE_PURGE
	CCR: cache purge (all entries invalidated).
#define	JO_SH2_SR_INTERRUPT_MASK
	Status register: interrupt mask bits (level 15 = all interrupts masked).
#define	JO_SH2_SR_INTERRUPTS_ON
	Status register: all interrupts enabled.
#define	JO_SH2_FRT_TIER
	Free running timer: interrupt enable register.
#define	JO_SH2_FRT_FTCSR
	Free running timer: control/status register.
#define	JO_SH2_FRT_TIER_NO_INTERRUPT
	TIER: all FRT interrupts disabled (bit 0 is always 1).
#define	JO_SH2_FRT_FTCSR_ICF
	FTCSR: input capture flag.
#define	JO_SH2_FRT_FTCSR_OCFA
	FTCSR: output compare flag A.
#define	JO_SH2_FRT_TIER_ICIE
	TIER: input capture interrupt enabled.
#define	JO_SH2_FRT_TIER_OCIAE
	TIER: output compare interrupt A enabled.
#define	JO_SH2_FRT_OCRAH
	Free running timer: output compare register A (high byte, see JO_SH2_FRT_TOCR).
#define	JO_SH2_FRT_OCRAL
	Free running timer: output compare register A (low byte, written last).
#define	JO_SH2_FRT_TOCR
	Free running timer: timer output compare control register.
#define	JO_SH2_FRT_TOCR_OCRA
	TOCR: output compare register A selected (bits 7 to 5 are always 1).
#define	JO_SH2_IPRB
	Interrupt controller: interrupt priority level setting register B (bits 11 to 8: free running timer).
#define	JO_SH2_VCRC
	Interrupt controller: vector number setting register C (bits 6 to 0: free running timer output compare).
#define	JO_SH2_DVSR
	Division unit: divisor register.
#define	JO_SH2_DVDNT
	Division unit: dividend register (32 bits division).
#define	JO_SH2_DVDNTH
	Division unit: dividend register high (64 bits division).
#define	JO_SH2_DVDNTL
	Division unit: dividend register low (64 bits division, writing starts the division, the quotient is read here).
#define	JO_SH2_SAR0
	DMA controller channel 0: source address.
#define	JO_SH2_DAR0
	DMA controller channel 0: destination address.
#define	JO_SH2_TCR0
	DMA controller channel 0: transfer count (in transfer units).
#define	JO_SH2_CHCR0
	DMA controller channel 0: channel control register.
#define	JO_SH2_DMAOR
	DMA controller: operation register.
#define	JO_SH2_CHCR_DEST_INCREMENT
	CHCR: destination address incremented.
#define	JO_SH2_CHCR_SRC_INCREMENT
	CHCR: source address incremented.
#define	JO_SH2_CHCR_SIZE_8
	CHCR: transfer unit (byte).
#define	JO_SH2_CHCR_SIZE_16
	CHCR: transfer unit (word).
#define	JO_SH2_CHCR_SIZE_32
	CHCR: transfer unit (long word).
#define	JO_SH2_CHCR_AUTO_REQUEST
	CHCR: auto request (the transfer starts as soon as the channel is enabled, cycle steal mode).
#define	JO_SH2_CHCR_TRANSFER_END
	CHCR: transfer end flag.
#define	JO_SH2_CHCR_ENABLE
	CHCR: channel enabled.
#define	JO_SH2_DMAOR_ENABLE
	DMAOR: DMA enabled for all the channels.
#define	JO_SH2_CACHE_PURGE_AREA
	Cache: associative purge of the line of an address (write 0 at JO_SH2_CACHE_PURGE_AREA \| address).
#define	JO_SH2_CACHE_LINE_SIZE
	Cache: line size.
#define	JO_SOUND_RAM
	Sound RAM (512 kilobytes).
#define	JO_SCSP_SLOT(SLOT, OFFSET)
	SCSP slot register.
#define	JO_SCSP_COMMON(OFFSET)
	SCSP common control register.
#define	JO_SCSP_SLOT_COUNT
	SCSP slot count.
#define	JO_SCSP_SLOT_CONTROL
	Key on, loop control, 8 bits PCM, start address (high bits).
#define	JO_SCSP_SLOT_START_ADDRESS
	Start address (low 16 bits).
#define	JO_SCSP_SLOT_LOOP_START
	Loop start address (in samples).
#define	JO_SCSP_SLOT_LOOP_END
	Loop end address (in samples).
#define	JO_SCSP_SLOT_ENVELOPE_ATTACK
	Envelope: decay 2 rate, decay 1 rate, attack rate.
#define	JO_SCSP_SLOT_ENVELOPE_RELEASE
	Envelope: key rate scaling, decay level, release rate.
#define	JO_SCSP_SLOT_TOTAL_LEVEL
	Total level (attenuation).
#define	JO_SCSP_SLOT_MODULATION
	Modulation.
#define	JO_SCSP_SLOT_PITCH
	Pitch (octave and frequency number).
#define	JO_SCSP_SLOT_LFO
	LFO.
#define	JO_SCSP_SLOT_DSP_INPUT
	DSP input.
#define	JO_SCSP_SLOT_MIXER
	Direct and effect send levels and pans.
#define	JO_SCSP_KEY_ON_EXECUTE
	Execute key on/off for all slots.
#define	JO_SCSP_KEY_ON
	Key on.
#define	JO_SCSP_KEY_MASK
	Bits not related to the key on/off.
#define	JO_SCSP_LOOP_NORMAL
	Normal loop.
#define	JO_SCSP_PCM_8BITS
	8 bits PCM (16 bits otherwise)
#define	JO_SCSP_START_ADDRESS_HIGH(ADDR)
	Start address high bits (address >> 16).
#define	JO_SCSP_START_ADDRESS_LOW(ADDR)
	Start address low bits.
#define	JO_SCSP_SOURCE_NOISE
	Sound source: the noise generator (SSCTL = 1) instead of the sound RAM.
#define	JO_SCSP_ENVELOPE_ATTACK(AR, D1R, D2R)
	Envelope register 0x08: decay 2 rate (bits 15-11), decay 1 rate (bits 10-6), attack rate (bits 4-0).
#define	JO_SCSP_ENVELOPE_RELEASE(RR)
	Envelope register 0x0A: no key rate scaling (KRS = 0xF: the rates don't depend on the pitch), decay level 0, release rate.
#define	JO_SCSP_MODULATION(MDL, X, Y)
	Modulation register: modulation level (MDL, 0 to 15: 5 and more modulate), the 2 inputs (MDXSL, MDYSL: the stack of the outputs of the slots: 32 + n is the slot + n, one sample before).
#define	JO_SCSP_LFO(LFOF, ALFOWS, ALFOS)
	LFO register: frequency (LFOF: 0 to 31, 0.17 to 96 Hz), the waveform and the depth of the amplitude LFO.
#define	JO_SCSP_LFO_TRIANGLE
	LFO waveform: triangle.
#define	JO_SCSP_DSP_SEND(ISEL, IMXL)
	DSP input register: the mix of the DSP the slot goes to (ISEL, 0 to 15) and its level (IMXL: 0 none, 1 to 7: -36 to 0 dB).
#define	JO_SCSP_ATTACK_RATE_MAX
	Envelope: attack rate maximum (no attack).
#define	JO_SCSP_RELEASE_RATE_MAX
	Envelope: release rate maximum (immediate release).
#define	JO_SCSP_PITCH(OCT, FNS)
	Pitch register value.
#define	JO_SCSP_FNS_MAX
	Maximum frequency number.
#define	JO_SCSP_FNS_PER_OCTAVE
	Frequency number count per octave.
#define	JO_SCSP_BASE_SAMPLING_RATE
	Sampling rate at octave 0 and frequency number 0 (Hz).
#define	JO_SCSP_TOTAL_LEVEL(VOLUME)
	Total level register value (attenuation) from a volume.
#define	JO_SCSP_DIRECT_LEVEL(LEVEL)
	Direct send level (0 to 7).
#define	JO_SCSP_DIRECT_PAN(PAN)
	Direct pan (5 bits, see JO_SCSP_PAN_xxx).
#define	JO_SCSP_EFFECT_LEVEL(LEVEL)
	Effect send level (0 to 7).
#define	JO_SCSP_EFFECT_PAN(PAN)
	Effect pan (5 bits, see JO_SCSP_PAN_xxx).
#define	JO_SCSP_PAN_CENTER
	Pan: center.
#define	JO_SCSP_PAN_LEFT_SIDE
	Pan: left side flag (bits 3-0: attenuation of the other side).
#define	JO_SCSP_PAN_RIGHT
	Pan: full right.
#define	JO_SCSP_PAN_LEFT
	Pan: full left.
#define	JO_SCSP_LEVEL_MAX
	Maximum send level.
#define	JO_SCSP_CDDA_LEFT_SLOT
	Slot used for the CD audio left channel (EXTS input).
#define	JO_SCSP_CDDA_RIGHT_SLOT
	Slot used for the CD audio right channel (EXTS input).
#define	JO_SCSP_COMMON_MASTER_VOLUME
	Master volume register (MVOL bits 0-3, 16 bits DAC, 4 Mbits sound RAM).
#define	JO_SCSP_COMMON_RING_BUFFER
	Ring buffer of the DSP: its length (bits 8-7: 8K, 16K, 32K, 64K words) and its address (bits 6-0: 8 KB units).
#define	JO_SCSP_DSP_AREA
	The registers of the DSP of the SCSP: coefficients (0x700), memory addresses (0x780), program (0x800, 128 steps of 4 words).
#define	JO_SCSP_DSP_AREA_SIZE
#define	JO_SCSP_DSP_COEF
	The coefficients of the DSP (64 words: 13 bits, bits 15-3), offset in JO_SCSP_DSP_AREA.
#define	JO_SCSP_DSP_ADDRESS
	The memory addresses of the DSP (32 words), offset in JO_SCSP_DSP_AREA.
#define	JO_SCSP_DSP_PROGRAM
	The program of the DSP (128 steps of 4 words), offset in JO_SCSP_DSP_AREA.
#define	JO_SCSP_DSP_FLOAT_ZERO
	0 in the float format of the ring buffer of the DSP (exponent 12; 0x0000 is +0.5)
#define	JO_SCSP_RING_BUFFER(WORDS, ADDR)
	The ring buffer register (JO_SCSP_COMMON_RING_BUFFER).
#define	JO_SCSP_MASTER_VOLUME_MASK
	Master volume bits.
#define	JO_SCSP_MASTER_VOLUME_MAX
	Maximum master volume.
#define	JO_IS_PTR_INSIDE_USER_RAM_AREA(PTR)
	Check if the pointer is inside user area WORK RAM.
#define	JO_IS_ARRAY_INSIDE_USER_RAM_AREA(ARRAY)
	Check if the array is inside user area WORK RAM.

Functions
static __jo_force_inline unsigned short	__jo_scsp_pitch (unsigned int rate)
	Pitch register value for a sampling rate (Internal usage).

Variables
unsigned int	_jo_work_start
	Start of the engine work area (VDP1 command lists, 3D buffers, etc): after the program and its data (see jo.linker).

Detailed Description

Jo Engine Sega Saturn constants (addresses, memory sizes, etc).

Author: Johannes Fetz

Bug: No known bugs.

Macro Definition Documentation

◆ JO_BIOS_CHANGE_SYSTEM_CLOCK

#define JO_BIOS_CHANGE_SYSTEM_CLOCK ( CLOCK )

Boot ROM routine that changes the system clock (SYS_CHGSYSCK): 0 = 26.8 MHz (320 and 640 pixels width), 1 = 28.6 MHz (352 and 704 pixels width). The VDPs, the SCU and the slave CPU are reset.

◆ JO_BIOS_SCU_IMS

#define JO_BIOS_SCU_IMS

Copy of the SCU interrupt mask kept by the BIOS (SYS_GETSCUIM): the interrupt handlers of the BIOS write it to JO_SCU_IMS when they return, it must always be equal to the mask written to JO_SCU_IMS.

◆ JO_BIOS_SYSTEM_CLOCK_320

#define JO_BIOS_SYSTEM_CLOCK_320

System clock of the 320 and 640 pixels width modes (see JO_BIOS_CHANGE_SYSTEM_CLOCK()).

◆ JO_BIOS_SYSTEM_CLOCK_352

#define JO_BIOS_SYSTEM_CLOCK_352

System clock of the 352 and 704 pixels width modes (see JO_BIOS_CHANGE_SYSTEM_CLOCK()).

◆ JO_CACHE_THROUGH

#define JO_CACHE_THROUGH ( ADDR )

Cache-through mirror of an address (to share data between the two CPU).

◆ JO_IS_ARRAY_INSIDE_USER_RAM_AREA

#define JO_IS_ARRAY_INSIDE_USER_RAM_AREA ( ARRAY )

Check if the array is inside user area WORK RAM.

Parameters

ARRAY An array like char[256]

◆ JO_IS_PTR_INSIDE_USER_RAM_AREA

#define JO_IS_PTR_INSIDE_USER_RAM_AREA ( PTR )

Check if the pointer is inside user area WORK RAM.

Parameters

PTR Pointer

◆ JO_RAM_CARTRIDGE_32MBITS_SIZE

#define JO_RAM_CARTRIDGE_32MBITS_SIZE

Extended RAM cartridge 4 MB: size.

◆ JO_RAM_CARTRIDGE_8MBITS_BANK2_ADDRESS

#define JO_RAM_CARTRIDGE_8MBITS_BANK2_ADDRESS

Extended RAM cartridge 1 MB: second bank address.

◆ JO_RAM_CARTRIDGE_8MBITS_BANK_SIZE

#define JO_RAM_CARTRIDGE_8MBITS_BANK_SIZE

Extended RAM cartridge 1 MB: size of a bank.

◆ JO_RAM_CARTRIDGE_ADDRESS

#define JO_RAM_CARTRIDGE_ADDRESS

Extended RAM cartridge: RAM address.

◆ JO_RAM_CARTRIDGE_AREF

#define JO_RAM_CARTRIDGE_AREF

A-bus refresh for the extended RAM cartridge (JO_SCU_AREF).

◆ JO_RAM_CARTRIDGE_ASR0

#define JO_RAM_CARTRIDGE_ASR0

A-bus timings for the extended RAM cartridge (JO_SCU_ASR0).

◆ JO_RAM_CARTRIDGE_ENABLE

#define JO_RAM_CARTRIDGE_ENABLE

Extended RAM cartridge: write 1 to enable the RAM (16 bits write).

◆ JO_RAM_CARTRIDGE_ID

#define JO_RAM_CARTRIDGE_ID

Extended RAM cartridge identifier.

◆ JO_RAM_CARTRIDGE_ID_32MBITS

#define JO_RAM_CARTRIDGE_ID_32MBITS

Extended RAM cartridge identifier: 4 MB (32 Mbits).

◆ JO_RAM_CARTRIDGE_ID_8MBITS

#define JO_RAM_CARTRIDGE_ID_8MBITS

Extended RAM cartridge identifier: 1 MB (8 Mbits).

◆ JO_SCSP_ATTACK_RATE_MAX

#define JO_SCSP_ATTACK_RATE_MAX

Envelope: attack rate maximum (no attack).

◆ JO_SCSP_BASE_SAMPLING_RATE

#define JO_SCSP_BASE_SAMPLING_RATE

Sampling rate at octave 0 and frequency number 0 (Hz).

◆ JO_SCSP_CDDA_LEFT_SLOT

#define JO_SCSP_CDDA_LEFT_SLOT

Slot used for the CD audio left channel (EXTS input).

◆ JO_SCSP_CDDA_RIGHT_SLOT

#define JO_SCSP_CDDA_RIGHT_SLOT

Slot used for the CD audio right channel (EXTS input).

◆ JO_SCSP_COMMON

#define JO_SCSP_COMMON ( OFFSET )

SCSP common control register.

◆ JO_SCSP_COMMON_MASTER_VOLUME

#define JO_SCSP_COMMON_MASTER_VOLUME

Master volume register (MVOL bits 0-3, 16 bits DAC, 4 Mbits sound RAM).

◆ JO_SCSP_COMMON_RING_BUFFER

#define JO_SCSP_COMMON_RING_BUFFER

Ring buffer of the DSP: its length (bits 8-7: 8K, 16K, 32K, 64K words) and its address (bits 6-0: 8 KB units).

◆ JO_SCSP_DIRECT_LEVEL

#define JO_SCSP_DIRECT_LEVEL ( LEVEL )

Direct send level (0 to 7).

◆ JO_SCSP_DIRECT_PAN

#define JO_SCSP_DIRECT_PAN ( PAN )

Direct pan (5 bits, see JO_SCSP_PAN_xxx).

◆ JO_SCSP_DSP_ADDRESS

#define JO_SCSP_DSP_ADDRESS

The memory addresses of the DSP (32 words), offset in JO_SCSP_DSP_AREA.

◆ JO_SCSP_DSP_AREA

#define JO_SCSP_DSP_AREA

The registers of the DSP of the SCSP: coefficients (0x700), memory addresses (0x780), program (0x800, 128 steps of 4 words).

◆ JO_SCSP_DSP_AREA_SIZE

#define JO_SCSP_DSP_AREA_SIZE

◆ JO_SCSP_DSP_COEF

#define JO_SCSP_DSP_COEF

The coefficients of the DSP (64 words: 13 bits, bits 15-3), offset in JO_SCSP_DSP_AREA.

◆ JO_SCSP_DSP_FLOAT_ZERO

#define JO_SCSP_DSP_FLOAT_ZERO

0 in the float format of the ring buffer of the DSP (exponent 12; 0x0000 is +0.5)

◆ JO_SCSP_DSP_PROGRAM

#define JO_SCSP_DSP_PROGRAM

The program of the DSP (128 steps of 4 words), offset in JO_SCSP_DSP_AREA.

◆ JO_SCSP_DSP_SEND

#define JO_SCSP_DSP_SEND	(		ISEL,
			IMXL )

DSP input register: the mix of the DSP the slot goes to (ISEL, 0 to 15) and its level (IMXL: 0 none, 1 to 7: -36 to 0 dB).

◆ JO_SCSP_EFFECT_LEVEL

#define JO_SCSP_EFFECT_LEVEL ( LEVEL )

Effect send level (0 to 7).

◆ JO_SCSP_EFFECT_PAN

#define JO_SCSP_EFFECT_PAN ( PAN )

Effect pan (5 bits, see JO_SCSP_PAN_xxx).

◆ JO_SCSP_ENVELOPE_ATTACK

#define JO_SCSP_ENVELOPE_ATTACK	(	AR,
		D1R,
		D2R )

Envelope register 0x08: decay 2 rate (bits 15-11), decay 1 rate (bits 10-6), attack rate (bits 4-0).

◆ JO_SCSP_ENVELOPE_RELEASE

#define JO_SCSP_ENVELOPE_RELEASE ( RR )

Envelope register 0x0A: no key rate scaling (KRS = 0xF: the rates don't depend on the pitch), decay level 0, release rate.

◆ JO_SCSP_FNS_MAX

#define JO_SCSP_FNS_MAX

Maximum frequency number.

◆ JO_SCSP_FNS_PER_OCTAVE

#define JO_SCSP_FNS_PER_OCTAVE

Frequency number count per octave.

◆ JO_SCSP_KEY_MASK

#define JO_SCSP_KEY_MASK

Bits not related to the key on/off.

◆ JO_SCSP_KEY_ON

#define JO_SCSP_KEY_ON

Key on.

◆ JO_SCSP_KEY_ON_EXECUTE

#define JO_SCSP_KEY_ON_EXECUTE

Execute key on/off for all slots.

◆ JO_SCSP_LEVEL_MAX

#define JO_SCSP_LEVEL_MAX

Maximum send level.

◆ JO_SCSP_LFO

#define JO_SCSP_LFO	(	LFOF,
		ALFOWS,
		ALFOS )

LFO register: frequency (LFOF: 0 to 31, 0.17 to 96 Hz), the waveform and the depth of the amplitude LFO.

◆ JO_SCSP_LFO_TRIANGLE

#define JO_SCSP_LFO_TRIANGLE

LFO waveform: triangle.

◆ JO_SCSP_LOOP_NORMAL

#define JO_SCSP_LOOP_NORMAL

Normal loop.

◆ JO_SCSP_MASTER_VOLUME_MASK

#define JO_SCSP_MASTER_VOLUME_MASK

Master volume bits.

◆ JO_SCSP_MASTER_VOLUME_MAX

#define JO_SCSP_MASTER_VOLUME_MAX

Maximum master volume.

◆ JO_SCSP_MODULATION

#define JO_SCSP_MODULATION	(	MDL,
		X,
		Y )

Modulation register: modulation level (MDL, 0 to 15: 5 and more modulate), the 2 inputs (MDXSL, MDYSL: the stack of the outputs of the slots: 32 + n is the slot + n, one sample before).

◆ JO_SCSP_PAN_CENTER

#define JO_SCSP_PAN_CENTER

Pan: center.

◆ JO_SCSP_PAN_LEFT

#define JO_SCSP_PAN_LEFT

Pan: full left.

◆ JO_SCSP_PAN_LEFT_SIDE

#define JO_SCSP_PAN_LEFT_SIDE

Pan: left side flag (bits 3-0: attenuation of the other side).

◆ JO_SCSP_PAN_RIGHT

#define JO_SCSP_PAN_RIGHT

Pan: full right.

◆ JO_SCSP_PCM_8BITS

#define JO_SCSP_PCM_8BITS

8 bits PCM (16 bits otherwise)

◆ JO_SCSP_PITCH

#define JO_SCSP_PITCH	(		OCT,
			FNS )

Pitch register value.

Parameters

OCT	Octave (-8 to 7)
FNS	Frequency number (0 to 1023): frequency = 44100 * 2^OCT * (1 + FNS / 1024)

◆ JO_SCSP_RELEASE_RATE_MAX

#define JO_SCSP_RELEASE_RATE_MAX

Envelope: release rate maximum (immediate release).

◆ JO_SCSP_RING_BUFFER

#define JO_SCSP_RING_BUFFER	(		WORDS,
			ADDR )

The ring buffer register (JO_SCSP_COMMON_RING_BUFFER).

Parameters

WORDS	Length: 8192, 16384, 32768 or 65536 words
ADDR	Address in the sound RAM (8 KB aligned)

◆ JO_SCSP_SLOT

#define JO_SCSP_SLOT	(		SLOT,
			OFFSET )

SCSP slot register.

◆ JO_SCSP_SLOT_CONTROL

#define JO_SCSP_SLOT_CONTROL

Key on, loop control, 8 bits PCM, start address (high bits).

◆ JO_SCSP_SLOT_COUNT

#define JO_SCSP_SLOT_COUNT

SCSP slot count.

◆ JO_SCSP_SLOT_DSP_INPUT

#define JO_SCSP_SLOT_DSP_INPUT

DSP input.

◆ JO_SCSP_SLOT_ENVELOPE_ATTACK

#define JO_SCSP_SLOT_ENVELOPE_ATTACK

Envelope: decay 2 rate, decay 1 rate, attack rate.

◆ JO_SCSP_SLOT_ENVELOPE_RELEASE

#define JO_SCSP_SLOT_ENVELOPE_RELEASE

Envelope: key rate scaling, decay level, release rate.

◆ JO_SCSP_SLOT_LFO

#define JO_SCSP_SLOT_LFO

LFO.

◆ JO_SCSP_SLOT_LOOP_END

#define JO_SCSP_SLOT_LOOP_END

Loop end address (in samples).

◆ JO_SCSP_SLOT_LOOP_START

#define JO_SCSP_SLOT_LOOP_START

Loop start address (in samples).

◆ JO_SCSP_SLOT_MIXER

#define JO_SCSP_SLOT_MIXER

Direct and effect send levels and pans.

◆ JO_SCSP_SLOT_MODULATION

#define JO_SCSP_SLOT_MODULATION

Modulation.

◆ JO_SCSP_SLOT_PITCH

#define JO_SCSP_SLOT_PITCH

Pitch (octave and frequency number).

◆ JO_SCSP_SLOT_START_ADDRESS

#define JO_SCSP_SLOT_START_ADDRESS

Start address (low 16 bits).

◆ JO_SCSP_SLOT_TOTAL_LEVEL

#define JO_SCSP_SLOT_TOTAL_LEVEL

Total level (attenuation).

◆ JO_SCSP_SOURCE_NOISE

#define JO_SCSP_SOURCE_NOISE

Sound source: the noise generator (SSCTL = 1) instead of the sound RAM.

◆ JO_SCSP_START_ADDRESS_HIGH

#define JO_SCSP_START_ADDRESS_HIGH ( ADDR )

Start address high bits (address >> 16).

◆ JO_SCSP_START_ADDRESS_LOW

#define JO_SCSP_START_ADDRESS_LOW ( ADDR )

Start address low bits.

◆ JO_SCSP_TOTAL_LEVEL

#define JO_SCSP_TOTAL_LEVEL ( VOLUME )

Total level register value (attenuation) from a volume.

Parameters

VOLUME 0 (silent) to 127 (max)

◆ JO_SCU_AREF

#define JO_SCU_AREF

SCU A-bus refresh register.

◆ JO_SCU_ASR0

#define JO_SCU_ASR0

SCU A-bus set register 0 (CS0 and CS1 access timings).

◆ JO_SCU_DMA_ADD

#define JO_SCU_DMA_ADD ( N )

◆ JO_SCU_DMA_ADD_READ4_WRITE2

#define JO_SCU_DMA_ADD_READ4_WRITE2

SCU DMA add: read address + 4, write address + 2 (B-bus: VDP1, VDP2, sound).

◆ JO_SCU_DMA_COUNT

#define JO_SCU_DMA_COUNT ( N )

◆ JO_SCU_DMA_ENABLE

#define JO_SCU_DMA_ENABLE ( N )

◆ JO_SCU_DMA_ENABLE_START

#define JO_SCU_DMA_ENABLE_START

SCU DMA enable: enabled and started.

◆ JO_SCU_DMA_INDIRECT_END

#define JO_SCU_DMA_INDIRECT_END

SCU DMA indirect table: end of the table (read address of the last transfer).

◆ JO_SCU_DMA_MODE

#define JO_SCU_DMA_MODE ( N )

◆ JO_SCU_DMA_MODE_DIRECT

#define JO_SCU_DMA_MODE_DIRECT

SCU DMA mode: direct mode, started by JO_SCU_DMA_ENABLE_START.

◆ JO_SCU_DMA_MODE_INDIRECT

#define JO_SCU_DMA_MODE_INDIRECT

SCU DMA mode: indirect mode (table of transfers: byte count, write address, read address | 0x80000000 for the last one).

◆ JO_SCU_DMA_READ

#define JO_SCU_DMA_READ ( N )

SCU DMA level N (0 to 2): read address, write address (or indirect table), byte count, address add, enable, mode.

◆ JO_SCU_DMA_STATUS

#define JO_SCU_DMA_STATUS

SCU DMA status register.

◆ JO_SCU_DMA_STATUS_BUSY

#define JO_SCU_DMA_STATUS_BUSY ( N )

SCU DMA status: level N in operation.

◆ JO_SCU_DMA_WRITE

#define JO_SCU_DMA_WRITE ( N )

◆ JO_SCU_IMS

#define JO_SCU_IMS

SCU interrupt mask register.

◆ JO_SCU_INT_ALL

#define JO_SCU_INT_ALL

◆ JO_SCU_INT_HBLANK_IN

#define JO_SCU_INT_HBLANK_IN

◆ JO_SCU_INT_SMPC

#define JO_SCU_INT_SMPC

◆ JO_SCU_INT_SOUND

#define JO_SCU_INT_SOUND

◆ JO_SCU_INT_SPRITE_END

#define JO_SCU_INT_SPRITE_END

◆ JO_SCU_INT_TIMER0

#define JO_SCU_INT_TIMER0

◆ JO_SCU_INT_TIMER1

#define JO_SCU_INT_TIMER1

◆ JO_SCU_INT_VBLANK_IN

#define JO_SCU_INT_VBLANK_IN

SCU interrupt mask bits.

◆ JO_SCU_INT_VBLANK_OUT

#define JO_SCU_INT_VBLANK_OUT

◆ JO_SCU_IST

#define JO_SCU_IST

SCU interrupt status register.

◆ JO_SH2_CACHE_LINE_SIZE

#define JO_SH2_CACHE_LINE_SIZE

Cache: line size.

◆ JO_SH2_CACHE_PURGE_AREA

#define JO_SH2_CACHE_PURGE_AREA

Cache: associative purge of the line of an address (write 0 at JO_SH2_CACHE_PURGE_AREA | address).

◆ JO_SH2_CCR

#define JO_SH2_CCR

Cache control register.

◆ JO_SH2_CCR_CACHE_ENABLE

#define JO_SH2_CCR_CACHE_ENABLE

CCR: cache enabled.

◆ JO_SH2_CCR_CACHE_PURGE

#define JO_SH2_CCR_CACHE_PURGE

CCR: cache purge (all entries invalidated).

◆ JO_SH2_CHCR0

#define JO_SH2_CHCR0

DMA controller channel 0: channel control register.

◆ JO_SH2_CHCR_AUTO_REQUEST

#define JO_SH2_CHCR_AUTO_REQUEST

CHCR: auto request (the transfer starts as soon as the channel is enabled, cycle steal mode).

◆ JO_SH2_CHCR_DEST_INCREMENT

#define JO_SH2_CHCR_DEST_INCREMENT

CHCR: destination address incremented.

◆ JO_SH2_CHCR_ENABLE

#define JO_SH2_CHCR_ENABLE

CHCR: channel enabled.

◆ JO_SH2_CHCR_SIZE_16

#define JO_SH2_CHCR_SIZE_16

CHCR: transfer unit (word).

◆ JO_SH2_CHCR_SIZE_32

#define JO_SH2_CHCR_SIZE_32

CHCR: transfer unit (long word).

◆ JO_SH2_CHCR_SIZE_8

#define JO_SH2_CHCR_SIZE_8

CHCR: transfer unit (byte).

◆ JO_SH2_CHCR_SRC_INCREMENT

#define JO_SH2_CHCR_SRC_INCREMENT

CHCR: source address incremented.

◆ JO_SH2_CHCR_TRANSFER_END

#define JO_SH2_CHCR_TRANSFER_END

CHCR: transfer end flag.

◆ JO_SH2_DAR0

#define JO_SH2_DAR0

DMA controller channel 0: destination address.

◆ JO_SH2_DMAOR

#define JO_SH2_DMAOR

DMA controller: operation register.

◆ JO_SH2_DMAOR_ENABLE

#define JO_SH2_DMAOR_ENABLE

DMAOR: DMA enabled for all the channels.

◆ JO_SH2_DVDNT

#define JO_SH2_DVDNT

Division unit: dividend register (32 bits division).

◆ JO_SH2_DVDNTH

#define JO_SH2_DVDNTH

Division unit: dividend register high (64 bits division).

◆ JO_SH2_DVDNTL

#define JO_SH2_DVDNTL

Division unit: dividend register low (64 bits division, writing starts the division, the quotient is read here).

◆ JO_SH2_DVSR

#define JO_SH2_DVSR

Division unit: divisor register.

◆ JO_SH2_FRT_FTCSR

#define JO_SH2_FRT_FTCSR

Free running timer: control/status register.

◆ JO_SH2_FRT_FTCSR_ICF

#define JO_SH2_FRT_FTCSR_ICF

FTCSR: input capture flag.

◆ JO_SH2_FRT_FTCSR_OCFA

#define JO_SH2_FRT_FTCSR_OCFA

FTCSR: output compare flag A.

◆ JO_SH2_FRT_OCRAH

#define JO_SH2_FRT_OCRAH

Free running timer: output compare register A (high byte, see JO_SH2_FRT_TOCR).

◆ JO_SH2_FRT_OCRAL

#define JO_SH2_FRT_OCRAL

Free running timer: output compare register A (low byte, written last).

◆ JO_SH2_FRT_TIER

#define JO_SH2_FRT_TIER

Free running timer: interrupt enable register.

◆ JO_SH2_FRT_TIER_ICIE

#define JO_SH2_FRT_TIER_ICIE

TIER: input capture interrupt enabled.

◆ JO_SH2_FRT_TIER_NO_INTERRUPT

#define JO_SH2_FRT_TIER_NO_INTERRUPT

TIER: all FRT interrupts disabled (bit 0 is always 1).

◆ JO_SH2_FRT_TIER_OCIAE

#define JO_SH2_FRT_TIER_OCIAE

TIER: output compare interrupt A enabled.

◆ JO_SH2_FRT_TOCR

#define JO_SH2_FRT_TOCR

Free running timer: timer output compare control register.

◆ JO_SH2_FRT_TOCR_OCRA

#define JO_SH2_FRT_TOCR_OCRA

TOCR: output compare register A selected (bits 7 to 5 are always 1).

◆ JO_SH2_IPRB

#define JO_SH2_IPRB

Interrupt controller: interrupt priority level setting register B (bits 11 to 8: free running timer).

◆ JO_SH2_SAR0

#define JO_SH2_SAR0

DMA controller channel 0: source address.

◆ JO_SH2_SR_INTERRUPT_MASK

#define JO_SH2_SR_INTERRUPT_MASK

Status register: interrupt mask bits (level 15 = all interrupts masked).

◆ JO_SH2_SR_INTERRUPTS_ON

#define JO_SH2_SR_INTERRUPTS_ON

Status register: all interrupts enabled.

◆ JO_SH2_TCR0

#define JO_SH2_TCR0

DMA controller channel 0: transfer count (in transfer units).

◆ JO_SH2_VCRC

#define JO_SH2_VCRC

Interrupt controller: vector number setting register C (bits 6 to 0: free running timer output compare).

◆ JO_SOUND_RAM

#define JO_SOUND_RAM

Sound RAM (512 kilobytes).

◆ JO_VDP1_COPR

#define JO_VDP1_COPR

Return the current command table processed.

◆ JO_VDP1_EDSR

#define JO_VDP1_EDSR

Transfer end status.

◆ JO_VDP1_ENDR

#define JO_VDP1_ENDR

Force draw end.

◆ JO_VDP1_EWDR

#define JO_VDP1_EWDR

Erase/write color.

◆ JO_VDP1_EWLR

#define JO_VDP1_EWLR

Erase/write upper-left position.

◆ JO_VDP1_EWRR

#define JO_VDP1_EWRR

Erase/write lower-right position.

◆ JO_VDP1_FB

#define JO_VDP1_FB

VDP1 Frame buffer (256 kilobytes).

◆ JO_VDP1_FBCR

#define JO_VDP1_FBCR

Controls the frame buffer.

◆ JO_VDP1_LAST_REG

#define JO_VDP1_LAST_REG

Last VDP1 I/O register address.

◆ JO_VDP1_LOPR

#define JO_VDP1_LOPR

Return the last command table processed.

◆ JO_VDP1_MODR

#define JO_VDP1_MODR

Mode status.

◆ JO_VDP1_PTMR

#define JO_VDP1_PTMR

Plot trigger.

◆ JO_VDP1_REG

#define JO_VDP1_REG

VDP1 I/O register address.

◆ JO_VDP1_TEXTURE_DEF_BASE_ADDRESS

#define JO_VDP1_TEXTURE_DEF_BASE_ADDRESS

VDP1 Sprite base address.

◆ JO_VDP1_TVMR

#define JO_VDP1_TVMR

TV mode selection.

◆ JO_VDP1_USER_AREA_END_ADDR

#define JO_VDP1_USER_AREA_END_ADDR

VDP1 user area end address.

◆ JO_VDP1_USER_AREA_SIZE

#define JO_VDP1_USER_AREA_SIZE

VDP1 user area size.

◆ JO_VDP1_VRAM

#define JO_VDP1_VRAM

VDP1 VRAM (512 kilobytes).

◆ JO_VDP2_BANK_SIZE

#define JO_VDP2_BANK_SIZE

VDP2 VRAM Bank size (128 kilobytes).

◆ JO_VDP2_BGON

#define JO_VDP2_BGON

◆ JO_VDP2_BKTAL

#define JO_VDP2_BKTAL

◆ JO_VDP2_BKTAU

#define JO_VDP2_BKTAU

◆ JO_VDP2_BMPNA

#define JO_VDP2_BMPNA

◆ JO_VDP2_BMPNB

#define JO_VDP2_BMPNB

◆ JO_VDP2_CCCTL

#define JO_VDP2_CCCTL

◆ JO_VDP2_CCRLB

#define JO_VDP2_CCRLB

◆ JO_VDP2_CCRNA

#define JO_VDP2_CCRNA

◆ JO_VDP2_CCRNB

#define JO_VDP2_CCRNB

◆ JO_VDP2_CCRR

#define JO_VDP2_CCRR

◆ JO_VDP2_CCRSA

#define JO_VDP2_CCRSA

◆ JO_VDP2_CCRSB

#define JO_VDP2_CCRSB

◆ JO_VDP2_CCRSC

#define JO_VDP2_CCRSC

◆ JO_VDP2_CCRSD

#define JO_VDP2_CCRSD

◆ JO_VDP2_CHCTLA

#define JO_VDP2_CHCTLA

◆ JO_VDP2_CHCTLB

#define JO_VDP2_CHCTLB

◆ JO_VDP2_CLOFEN

#define JO_VDP2_CLOFEN

◆ JO_VDP2_CLOFSL

#define JO_VDP2_CLOFSL

◆ JO_VDP2_COAB

#define JO_VDP2_COAB

◆ JO_VDP2_COAG

#define JO_VDP2_COAG

◆ JO_VDP2_COAR

#define JO_VDP2_COAR

◆ JO_VDP2_COBB

#define JO_VDP2_COBB

◆ JO_VDP2_COBG

#define JO_VDP2_COBG

◆ JO_VDP2_COBR

#define JO_VDP2_COBR

◆ JO_VDP2_CRAM

#define JO_VDP2_CRAM

VDP2 Color RAM (4 kilobytes).

◆ JO_VDP2_CRAOFA

#define JO_VDP2_CRAOFA

◆ JO_VDP2_CRAOFB

#define JO_VDP2_CRAOFB

◆ JO_VDP2_CRAOFB_SPRITE_OFFSET

#define JO_VDP2_CRAOFB_SPRITE_OFFSET ( N )

CRAOFB: sprite color RAM address offset value (0 to 7).

◆ JO_VDP2_CRAOFB_SPRITE_OFFSET_MASK

#define JO_VDP2_CRAOFB_SPRITE_OFFSET_MASK

CRAOFB: sprite color RAM address offset bits.

◆ JO_VDP2_CYCA0L

#define JO_VDP2_CYCA0L

◆ JO_VDP2_CYCA0U

#define JO_VDP2_CYCA0U

◆ JO_VDP2_CYCA1L

#define JO_VDP2_CYCA1L

◆ JO_VDP2_CYCA1U

#define JO_VDP2_CYCA1U

◆ JO_VDP2_CYCB0L

#define JO_VDP2_CYCB0L

◆ JO_VDP2_CYCB0U

#define JO_VDP2_CYCB0U

◆ JO_VDP2_CYCB1L

#define JO_VDP2_CYCB1L

◆ JO_VDP2_CYCB1U

#define JO_VDP2_CYCB1U

◆ JO_VDP2_EXTEN

#define JO_VDP2_EXTEN

◆ JO_VDP2_HCNT

#define JO_VDP2_HCNT

◆ JO_VDP2_KTAOF

#define JO_VDP2_KTAOF

◆ JO_VDP2_KTCTL

#define JO_VDP2_KTCTL

◆ JO_VDP2_LAST_REG

#define JO_VDP2_LAST_REG

Last VDP2 I/O register address.

◆ JO_VDP2_LCTAL

#define JO_VDP2_LCTAL

◆ JO_VDP2_LCTAU

#define JO_VDP2_LCTAU

◆ JO_VDP2_LNCLEN

#define JO_VDP2_LNCLEN

◆ JO_VDP2_LSTA0L

#define JO_VDP2_LSTA0L

◆ JO_VDP2_LSTA0U

#define JO_VDP2_LSTA0U

◆ JO_VDP2_LSTA1L

#define JO_VDP2_LSTA1L

◆ JO_VDP2_LSTA1U

#define JO_VDP2_LSTA1U

◆ JO_VDP2_LWTA0L

#define JO_VDP2_LWTA0L

◆ JO_VDP2_LWTA0U

#define JO_VDP2_LWTA0U

◆ JO_VDP2_LWTA1L

#define JO_VDP2_LWTA1L

◆ JO_VDP2_LWTA1U

#define JO_VDP2_LWTA1U

◆ JO_VDP2_MPABN0

#define JO_VDP2_MPABN0

◆ JO_VDP2_MPABN1

#define JO_VDP2_MPABN1

◆ JO_VDP2_MPABN2

#define JO_VDP2_MPABN2

◆ JO_VDP2_MPABN3

#define JO_VDP2_MPABN3

◆ JO_VDP2_MPABRA

#define JO_VDP2_MPABRA

◆ JO_VDP2_MPABRB

#define JO_VDP2_MPABRB

◆ JO_VDP2_MPCDN0

#define JO_VDP2_MPCDN0

◆ JO_VDP2_MPCDN1

#define JO_VDP2_MPCDN1

◆ JO_VDP2_MPCDN2

#define JO_VDP2_MPCDN2

◆ JO_VDP2_MPCDN3

#define JO_VDP2_MPCDN3

◆ JO_VDP2_MPCDRA

#define JO_VDP2_MPCDRA

◆ JO_VDP2_MPCDRB

#define JO_VDP2_MPCDRB

◆ JO_VDP2_MPEFRA

#define JO_VDP2_MPEFRA

◆ JO_VDP2_MPEFRB

#define JO_VDP2_MPEFRB

◆ JO_VDP2_MPGHRA

#define JO_VDP2_MPGHRA

◆ JO_VDP2_MPGHRB

#define JO_VDP2_MPGHRB

◆ JO_VDP2_MPIJRA

#define JO_VDP2_MPIJRA

◆ JO_VDP2_MPIJRB

#define JO_VDP2_MPIJRB

◆ JO_VDP2_MPKLRA

#define JO_VDP2_MPKLRA

◆ JO_VDP2_MPKLRB

#define JO_VDP2_MPKLRB

◆ JO_VDP2_MPMNRA

#define JO_VDP2_MPMNRA

◆ JO_VDP2_MPMNRB

#define JO_VDP2_MPMNRB

◆ JO_VDP2_MPOFN

#define JO_VDP2_MPOFN

◆ JO_VDP2_MPOFR

#define JO_VDP2_MPOFR

◆ JO_VDP2_MPOPRA

#define JO_VDP2_MPOPRA

◆ JO_VDP2_MPOPRB

#define JO_VDP2_MPOPRB

◆ JO_VDP2_MZCTL

#define JO_VDP2_MZCTL

◆ JO_VDP2_NBG0_CEL_ADR

#define JO_VDP2_NBG0_CEL_ADR

◆ JO_VDP2_NBG0_MAP_ADR

#define JO_VDP2_NBG0_MAP_ADR

◆ JO_VDP2_NBG1_CEL_ADR

#define JO_VDP2_NBG1_CEL_ADR

◆ JO_VDP2_NBG1_MAP_ADR

#define JO_VDP2_NBG1_MAP_ADR

◆ JO_VDP2_OVPNRA

#define JO_VDP2_OVPNRA

◆ JO_VDP2_OVPNRB

#define JO_VDP2_OVPNRB

◆ JO_VDP2_PLSZ

#define JO_VDP2_PLSZ

◆ JO_VDP2_PNCN0

#define JO_VDP2_PNCN0

◆ JO_VDP2_PNCN1

#define JO_VDP2_PNCN1

◆ JO_VDP2_PNCN2

#define JO_VDP2_PNCN2

◆ JO_VDP2_PNCN3

#define JO_VDP2_PNCN3

◆ JO_VDP2_PNCR

#define JO_VDP2_PNCR

◆ JO_VDP2_PRINA

#define JO_VDP2_PRINA

◆ JO_VDP2_PRINB

#define JO_VDP2_PRINB

◆ JO_VDP2_PRIR

#define JO_VDP2_PRIR

◆ JO_VDP2_PRISA

#define JO_VDP2_PRISA

◆ JO_VDP2_PRISB

#define JO_VDP2_PRISB

◆ JO_VDP2_PRISC

#define JO_VDP2_PRISC

◆ JO_VDP2_PRISD

#define JO_VDP2_PRISD

◆ JO_VDP2_RAMCTL

#define JO_VDP2_RAMCTL

◆ JO_VDP2_REG

#define JO_VDP2_REG

VDP2 I/O register address.

◆ JO_VDP2_RESERVE

#define JO_VDP2_RESERVE

◆ JO_VDP2_RPMD

#define JO_VDP2_RPMD

◆ JO_VDP2_RPRCTL

#define JO_VDP2_RPRCTL

◆ JO_VDP2_RPTAL

#define JO_VDP2_RPTAL

◆ JO_VDP2_RPTAU

#define JO_VDP2_RPTAU

◆ JO_VDP2_SCRCTL

#define JO_VDP2_SCRCTL

◆ JO_VDP2_SCXDN0

#define JO_VDP2_SCXDN0

◆ JO_VDP2_SCXDN1

#define JO_VDP2_SCXDN1

◆ JO_VDP2_SCXIN0

#define JO_VDP2_SCXIN0

◆ JO_VDP2_SCXIN1

#define JO_VDP2_SCXIN1

◆ JO_VDP2_SCXN2

#define JO_VDP2_SCXN2

◆ JO_VDP2_SCXN3

#define JO_VDP2_SCXN3

◆ JO_VDP2_SCYDN0

#define JO_VDP2_SCYDN0

◆ JO_VDP2_SCYDN1

#define JO_VDP2_SCYDN1

◆ JO_VDP2_SCYIN0

#define JO_VDP2_SCYIN0

◆ JO_VDP2_SCYIN1

#define JO_VDP2_SCYIN1

◆ JO_VDP2_SCYN2

#define JO_VDP2_SCYN2

◆ JO_VDP2_SCYN3

#define JO_VDP2_SCYN3

◆ JO_VDP2_SDCTL

#define JO_VDP2_SDCTL

◆ JO_VDP2_SFCCMD

#define JO_VDP2_SFCCMD

◆ JO_VDP2_SFCODE

#define JO_VDP2_SFCODE

◆ JO_VDP2_SFPRMD

#define JO_VDP2_SFPRMD

◆ JO_VDP2_SFSEL

#define JO_VDP2_SFSEL

◆ JO_VDP2_SPCTL

#define JO_VDP2_SPCTL

◆ JO_VDP2_TVMD

#define JO_VDP2_TVMD

◆ JO_VDP2_TVSTAT

#define JO_VDP2_TVSTAT

◆ JO_VDP2_TVSTAT_PAL

#define JO_VDP2_TVSTAT_PAL

TVSTAT: PAL console (50 Hz).

◆ JO_VDP2_VCNT

#define JO_VDP2_VCNT

◆ JO_VDP2_VCSTAL

#define JO_VDP2_VCSTAL

◆ JO_VDP2_VCSTAU

#define JO_VDP2_VCSTAU

◆ JO_VDP2_VRAM

#define JO_VDP2_VRAM

VDP2 VRAM (512 kilobytes) = A0 + A1 + B0 + B1.

◆ JO_VDP2_VRAM_A0

#define JO_VDP2_VRAM_A0

VDP2 VRAM Bank A0 (128 kilobytes).

◆ JO_VDP2_VRAM_A1

#define JO_VDP2_VRAM_A1

VDP2 VRAM Bank A1 (128 kilobytes).

◆ JO_VDP2_VRAM_B0

#define JO_VDP2_VRAM_B0

VDP2 VRAM Bank B0 (128 kilobytes).

◆ JO_VDP2_VRAM_B1

#define JO_VDP2_VRAM_B1

VDP2 VRAM Bank B1 (128 kilobytes).

◆ JO_VDP2_VRSIZE

#define JO_VDP2_VRSIZE

◆ JO_VDP2_WCTLA

#define JO_VDP2_WCTLA

◆ JO_VDP2_WCTLB

#define JO_VDP2_WCTLB

◆ JO_VDP2_WCTLC

#define JO_VDP2_WCTLC

◆ JO_VDP2_WCTLD

#define JO_VDP2_WCTLD

◆ JO_VDP2_WPEX0

#define JO_VDP2_WPEX0

◆ JO_VDP2_WPEX1

#define JO_VDP2_WPEX1

◆ JO_VDP2_WPEY0

#define JO_VDP2_WPEY0

◆ JO_VDP2_WPEY1

#define JO_VDP2_WPEY1

◆ JO_VDP2_WPSX0

#define JO_VDP2_WPSX0

◆ JO_VDP2_WPSX1

#define JO_VDP2_WPSX1

◆ JO_VDP2_WPSY0

#define JO_VDP2_WPSY0

◆ JO_VDP2_WPSY1

#define JO_VDP2_WPSY1

◆ JO_VDP2_ZMCTL

#define JO_VDP2_ZMCTL

◆ JO_VDP2_ZMXDN0

#define JO_VDP2_ZMXDN0

◆ JO_VDP2_ZMXDN1

#define JO_VDP2_ZMXDN1

◆ JO_VDP2_ZMXIN0

#define JO_VDP2_ZMXIN0

◆ JO_VDP2_ZMXIN1

#define JO_VDP2_ZMXIN1

◆ JO_VDP2_ZMYDN0

#define JO_VDP2_ZMYDN0

◆ JO_VDP2_ZMYDN1

#define JO_VDP2_ZMYDN1

◆ JO_VDP2_ZMYIN0

#define JO_VDP2_ZMYIN0

◆ JO_VDP2_ZMYIN1

#define JO_VDP2_ZMYIN1

◆ JO_VECTOR_HBLANK_IN

#define JO_VECTOR_HBLANK_IN

◆ JO_VECTOR_SMPC

#define JO_VECTOR_SMPC

◆ JO_VECTOR_SOUND

#define JO_VECTOR_SOUND

◆ JO_VECTOR_SPRITE_END

#define JO_VECTOR_SPRITE_END

◆ JO_VECTOR_TIMER0

#define JO_VECTOR_TIMER0

◆ JO_VECTOR_TIMER1

#define JO_VECTOR_TIMER1

◆ JO_VECTOR_VBLANK_IN

#define JO_VECTOR_VBLANK_IN

SH-2 interrupt vectors used by the SCU.

◆ JO_VECTOR_VBLANK_OUT

#define JO_VECTOR_VBLANK_OUT

◆ JO_WORK_RAM_BOOT_ROM

#define JO_WORK_RAM_BOOT_ROM

ROM BIOS functions.

◆ JO_WORK_RAM_ENGINE_WORK

#define JO_WORK_RAM_ENGINE_WORK

◆ JO_WORK_RAM_ENGINE_WORK_ALIGNED_SECTION

#define JO_WORK_RAM_ENGINE_WORK_ALIGNED_SECTION

Engine work area, for a buffer aligned on a big boundary (placed first: no hole in the work area).

◆ JO_WORK_RAM_ENGINE_WORK_SECTION

#define JO_WORK_RAM_ENGINE_WORK_SECTION

Put a variable in the engine work area (not cleared by the program loader, cleared at startup).

◆ JO_WORK_RAM_HIGH

#define JO_WORK_RAM_HIGH

High work RAM (1 MB): the fastest memory of the CPUs.

◆ JO_WORK_RAM_LOW

#define JO_WORK_RAM_LOW

Low work RAM (1 MB): read much slower by the CPUs, no SCU DMA.

◆ JO_WORK_RAM_MASTER_CPU_DEFAULT_STACK

#define JO_WORK_RAM_MASTER_CPU_DEFAULT_STACK

Master CPU stack (used by the boot ROM).

◆ JO_WORK_RAM_SIZE

#define JO_WORK_RAM_SIZE

Size of the high or low work RAM.

◆ JO_WORK_RAM_SLAVE_CPU_STACK_AREA

#define JO_WORK_RAM_SLAVE_CPU_STACK_AREA

Slave CPU stack.

◆ JO_WORK_RAM_SLAVE_STACK_TOP

#define JO_WORK_RAM_SLAVE_STACK_TOP

Slave CPU stack (top).

◆ JO_WORK_RAM_STACK_BOTTOM

#define JO_WORK_RAM_STACK_BOTTOM

Master CPU stack (bottom, 16 KB, see jo.linker).

◆ JO_WORK_RAM_STACK_TOP

#define JO_WORK_RAM_STACK_TOP

Master CPU stack (top).

◆ JO_WORK_RAM_UNKNOWN_USAGE

#define JO_WORK_RAM_UNKNOWN_USAGE

IP.BIN and boot ROM work area.

◆ JO_WORK_RAM_USER_PROGRAM_AND_DATA

#define JO_WORK_RAM_USER_PROGRAM_AND_DATA

User area.

◆ JO_WORK_RAM_USER_PROGRAM_AND_DATA_END

#define JO_WORK_RAM_USER_PROGRAM_AND_DATA_END

End of the user area (the free high work RAM after the engine work area is given to jo_malloc()).

Function Documentation

◆ __jo_scsp_pitch()

__jo_force_inline unsigned short __jo_scsp_pitch ( unsigned int rate )

static

Pitch register value for a sampling rate (Internal usage).

Parameters

rate	Sampling rate in Hz (0 means JO_SCSP_BASE_SAMPLING_RATE)

Returns: Octave and frequency number (JO_SCSP_PITCH())

Remarks: frequency = 44100 * 2^OCT * (1 + FNS / 1024)

Variable Documentation

◆ _jo_work_start

unsigned int _jo_work_start

extern

Start of the engine work area (VDP1 command lists, 3D buffers, etc): after the program and its data (see jo.linker).

Macros

Functions

Variables

Detailed Description

Macro Definition Documentation

◆ JO_BIOS_CHANGE_SYSTEM_CLOCK

◆ JO_BIOS_SCU_IMS

◆ JO_BIOS_SYSTEM_CLOCK_320

◆ JO_BIOS_SYSTEM_CLOCK_352

◆ JO_CACHE_THROUGH

◆ JO_IS_ARRAY_INSIDE_USER_RAM_AREA

◆ JO_IS_PTR_INSIDE_USER_RAM_AREA

◆ JO_RAM_CARTRIDGE_32MBITS_SIZE

◆ JO_RAM_CARTRIDGE_8MBITS_BANK2_ADDRESS

◆ JO_RAM_CARTRIDGE_8MBITS_BANK_SIZE

◆ JO_RAM_CARTRIDGE_ADDRESS

◆ JO_RAM_CARTRIDGE_AREF

◆ JO_RAM_CARTRIDGE_ASR0

◆ JO_RAM_CARTRIDGE_ENABLE

◆ JO_RAM_CARTRIDGE_ID

◆ JO_RAM_CARTRIDGE_ID_32MBITS

◆ JO_RAM_CARTRIDGE_ID_8MBITS

◆ JO_SCSP_ATTACK_RATE_MAX

◆ JO_SCSP_BASE_SAMPLING_RATE

◆ JO_SCSP_CDDA_LEFT_SLOT

◆ JO_SCSP_CDDA_RIGHT_SLOT

◆ JO_SCSP_COMMON

◆ JO_SCSP_COMMON_MASTER_VOLUME

◆ JO_SCSP_COMMON_RING_BUFFER

◆ JO_SCSP_DIRECT_LEVEL

◆ JO_SCSP_DIRECT_PAN

◆ JO_SCSP_DSP_ADDRESS

◆ JO_SCSP_DSP_AREA

◆ JO_SCSP_DSP_AREA_SIZE

◆ JO_SCSP_DSP_COEF

◆ JO_SCSP_DSP_FLOAT_ZERO

◆ JO_SCSP_DSP_PROGRAM

◆ JO_SCSP_DSP_SEND

◆ JO_SCSP_EFFECT_LEVEL

◆ JO_SCSP_EFFECT_PAN

◆ JO_SCSP_ENVELOPE_ATTACK

◆ JO_SCSP_ENVELOPE_RELEASE

◆ JO_SCSP_FNS_MAX

◆ JO_SCSP_FNS_PER_OCTAVE

◆ JO_SCSP_KEY_MASK

◆ JO_SCSP_KEY_ON

◆ JO_SCSP_KEY_ON_EXECUTE

◆ JO_SCSP_LEVEL_MAX

◆ JO_SCSP_LFO

◆ JO_SCSP_LFO_TRIANGLE

◆ JO_SCSP_LOOP_NORMAL

◆ JO_SCSP_MASTER_VOLUME_MASK

◆ JO_SCSP_MASTER_VOLUME_MAX

◆ JO_SCSP_MODULATION

◆ JO_SCSP_PAN_CENTER

◆ JO_SCSP_PAN_LEFT

◆ JO_SCSP_PAN_LEFT_SIDE

◆ JO_SCSP_PAN_RIGHT

◆ JO_SCSP_PCM_8BITS

◆ JO_SCSP_PITCH

◆ JO_SCSP_RELEASE_RATE_MAX

◆ JO_SCSP_RING_BUFFER

◆ JO_SCSP_SLOT

◆ JO_SCSP_SLOT_CONTROL

◆ JO_SCSP_SLOT_COUNT

◆ JO_SCSP_SLOT_DSP_INPUT

◆ JO_SCSP_SLOT_ENVELOPE_ATTACK

◆ JO_SCSP_SLOT_ENVELOPE_RELEASE

◆ JO_SCSP_SLOT_LFO

◆ JO_SCSP_SLOT_LOOP_END

◆ JO_SCSP_SLOT_LOOP_START

◆ JO_SCSP_SLOT_MIXER

◆ JO_SCSP_SLOT_MODULATION

◆ JO_SCSP_SLOT_PITCH

◆ JO_SCSP_SLOT_START_ADDRESS

◆ JO_SCSP_SLOT_TOTAL_LEVEL

◆ JO_SCSP_SOURCE_NOISE

◆ JO_SCSP_START_ADDRESS_HIGH

◆ JO_SCSP_START_ADDRESS_LOW

◆ JO_SCSP_TOTAL_LEVEL